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- Path: news.cc.tut.fi!news
- From: mk59200@proffa.cc.tut.fi (Markku Kolkka)
- Newsgroups: comp.sys.amiga.misc
- Subject: Re: Speed: 68040 vs. 68060
- Date: 14 Mar 1996 17:11:12 +0200
- Organization: Tampere University of Technology
- Sender: mk59200@proffa.cc.tut.fi
- Distribution: world
- Message-ID: <xcju3zrg167.fsf@proffa.cc.tut.fi>
- References: <2924579182@tkhut.sojourn.com>
- <826011210@p1.f125.n201.z2.FidoNet.ftn> <4hoata$qsc@tkhut.sojourn.com>
- NNTP-Posting-Host: proffa.cc.tut.fi
- In-reply-to: mharrell@sojourn1.sojourn.com's message of 8 Mar 1996 03:52:10
- GMT
- X-Newsreader: Gnus v5.0.15
-
- >>>>> "Matt" == Matt Harrell <mharrell@sojourn1.sojourn.com> writes:
- > It allows simultaneous execution of two integer
- > instructions (or an integer and a float instruction) and one
- > branch instruction during each clock period. All integer
- > arithmetic or logical instructions are able to perform an
- > embedded load/store operation
- This is a really devious marketroid way to inflate the MIPS claims:
- they count an operation like ADD.x <ea>,Rn as TWO operations because
- of the "embedded load". Of course a RISC CPU would need two
- instructions for this, but I think this is just another reason to
- forget all MIPS values as meaningless marketing hype.
-
- --
- Markku Kolkka
- mk59200@cc.tut.fi
-